ADC Clock and TCXO Leakage

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whsky
Posts: 1
Joined: Wed Sep 18, 2024 2:39 pm

ADC Clock and TCXO Leakage

Post by whsky »

Hi, I'm having some trouble with my xA9. As I tune through pretty much any band, I see spurs whipping around all over the place. I'm pretty sure these are harmonics of the ADC clock and TCXO. For example, if I set the sample rate to be 56MSps, and tune to the neighborhood of 115MHz, I'll see one big spur at 112MHz (56 * 2), and a grouping of them centered around 115.2MHz (38.4 * 3) that will cluster closer together the more I tune the center frequency towards 115.2, ultimately disappearing when reaching that frequency.

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If these were 2-3db blips above the noise it would be ok, but these are like 25-30db above. They will go away if I turn the gain down from 60 to 12 or below, but then I get massive spectral side lobes, which I understand is a result from the sigma-delta ADC.

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The attached screenshots from SDR++. What can I do to mitigate this? I'm not very familiar with the details of the BladeRF 2.0 architecture or that of the AD9361. Could this be a config issue, or is it just inherent in the system? Thanks!

Reported by bladerf-cli:

Code: Select all

bladeRF> info

  Board:                    Nuand bladeRF 2.0 (bladerf2)
  Serial #:                 17eb31c937894d4aa6187b94b6b3b9a4
  VCTCXO DAC calibration:   0x1f4b
  FPGA size:                301 KLE
  FPGA loaded:              yes
  Flash size:               128 Mbit
  USB bus:                  4
  USB address:              1
  USB speed:                SuperSpeed
  Backend:                  libusb
  Instance:                 0

bladeRF> version

  bladeRF-cli version:        1.9.0
  libbladeRF version:         2.5.0

  Firmware version:           2.4.0-git-a3d5c55f
  FPGA version:               0.15.0 (configured by USB host)
sabrina23
Posts: 3
Joined: Wed Sep 25, 2024 7:14 pm

Re: ADC Clock and TCXO Leakage

Post by sabrina23 »

As you mentioned, reducing the gain helps decrease the spur levels, but at the cost of increasing side lobes due to the sigma-delta ADC's characteristics. I recommend finding a middle ground in gain settings that minimizes spurs without overly compromising dynamic range. Sometimes a gain between your current settings (like around 24-30 dB) might yield better results.
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