Operating LMS6002D From Fpga

[mefila]

Hi fellow developers!
I am trying to run my own application based on fpga, so far I succeeded in sending and receiving information via spi bus and calibrating LMS6002D, now I am intended to receive some actual signals, however there are some questions I need to ask:

1-)Is si5338 functioning by all means on power-on or do I have to build an I2C interface and learn to control si5338, by the way all I want is a decent clock signal(and it would be perfect if I knew the frequency) for LMS_RX_CLK, which is also used as an ADC clock as I understand.

2-)The lms_rx_clk signal does not pass through fpga, but we can reach lms_rx_clk_out; does LMS6002D serve this clock output regardless of its state, or do we have to enable the RX module first, if we are suppposed to enable rx module, is it by setting lms_rxen or changing SRXEN register in LMS memory?

3-) And final question: If we happen to reach LMS_RX_CLK_OUT signal, can we use it as ADC clock safely, is there a significant latency between rx_clk and rx_clk_out.

I know some of them are very basic but I think some other users can also use the answers in future.

[bpadalino]

1-)Is si5338 functioning by all means on power-on or do I have to build an I2C interface and learn to control si5338, by the way all I want is a decent clock signal(and it would be perfect if I knew the frequency) for LMS_RX_CLK, which is also used as an ADC clock as I understand.

I believe you need to enable the RX clock from the Si5338 before it will be sent out to the ADC. The clock rate of the main VCTCXO is 38.4MHz which can be trimmed using the trimdac that hangs off the FPGA. We tried to make the si5338.c as agnostic as possible and able to run on the NIOS processor. The same is for lms.c. You just need to replace lms_write() and lms_read() with something that works I believe.

2-)The lms_rx_clk signal does not pass through fpga, but we can reach lms_rx_clk_out; does LMS6002D serve this clock output regardless of its state, or do we have to enable the RX module first, if we are suppposed to enable rx module, is it by setting lms_rxen or changing SRXEN register in LMS memory?

You definitely need to enable it or else it won't come out.

3-) And final question: If we happen to reach LMS_RX_CLK_OUT signal, can we use it as ADC clock safely, is there a significant latency between rx_clk and rx_clk_out.

Yes - checking out the LMS6002D datasheet there is a section on page 2 discussing RX_CLK_OUT:

The receive clock, RX_CLK, is provided off chip at the RX_CLK_OUT pin and can be used to synchronise with the baseband digital receive data sampling clock.

Let us know if there are any other issues for you. If you are still using a NIOS processor inside of the FPGA, you might be able to just pull in the lms.c and si5338.c files to your project and use them wholesale. Like I said, we tried very hard to not use floating point so the free NIOS core could be used headless.

[mefila]

Thanks a lot for all this information. I am not using nios system, since I will need a lot of space in FPGA. But I can probably build an I2C connection and control si5338.
I will probably notify when I am done or definitely notify if I have another problem, and if you want, I can put the VHDL coded I2C connection in the repository too.

[mefila]

Hi Fellows

I am done with I2C configuration, and succesfully generated an RX clcok for LMS6002D, however I have faced another problem( actually I am facing thousand problems everyday, I got stuck at this one). I have been trying to receive data at 900MHz generated and supplied directly from a signal generator(no antenna, just a cable). I have calculated the necessary variables such as FREQSEL, NINT and NFRAC and followed the instructions on LMS6002D programming and calibration guide (http://www.limemicro.com/download/LMS60 ... -1.1r1.pdf) in section tx/rx pll (page 27-28-29-30). According to the documentation V_tune values should go as "10"- "00" - "01" as I increased the VCOCAP value, and I should pick the VCOCAP value that corresponds the middle of the "00" range. In my case the v_tune value is constant "00" . And I have tested the system with each 512 data that can be written to NINT. What might be wrong? My favorite suspect is PLL clock's voltage, however, I was succesfully receiving data with hostedx40 code so it should be fine. But was it fine from initialization?

-- Is PLL clock set ready from initialization, or should I configure it too?
-- Can the experienced FPGA wizards tell me the possible mistakes that can be done during receiving, I am out of ideas and probably missing something very important?
-- Should I configure VOVCOREG and chage BYPCOREG to not-bypassed from bypassed?

Sorry if it is a long and detailed question but I think I have to write a comprehensive post. Because most people are asleep when I am writing, so I have to wait until tomorrow to see an answer and comment about it.

Thanks for reading, more thanks for replying.

Mefila

[Montezuma]

Out of curiosity, which bladeRF do you have(x115 or x40)?

[mefila]

I am using x40, but I have both of them, if this problem does not happen with x115 , I can use it too. For now I am not using x115 in case I damage the board

[bpadalino]

So what I would recommend is to get something working with the hostedx40 code in the bladeRF-cli. Receive some samples and make sure the constellation or signal is there and what you want it to be.

I would then use the 'peek lms 0 128' command to read the LMS, starting at address 0 and for 128 registers. This will dump the entire register map our for you.

I would then compare these values to the values you're seeing at the end of configuring your device from the NIOS.

Have you tried using the code in lms.c or si5338.c in the NIOS directly? We tried very hard to make sure it didn't use any double or floats.

You could hopefully use that as it is to manipulate each one of those. Then you would just need to create a bladerf_si5338_read/write function as well as bladerf_lms_read/write function.

Let us know how it goes. Also - how difficult was it for you to do your own i2c? It seems like there was some time inbetween posts?

[mefila]

Wow dude!! I owe you one. I did not know anything about that command 'peek lms 0 128'.

Congrats on making the values all in fixed-point, however, unfortunately I do not use NIOS system, I guess my project will need a lot of space and I need some fast(really fast) processing after sampling the data's.

I have already build two modules, one for controlling the i2c bus and the other is for spi bus. Spi was a piece of cake but I couldn't handle the bidirectional pins in i2c.
And the problem that slave was stretching the clock(somebody should teach that slave some manners). So I configured an i2c module I found from digi-key, our i2c communication is not a generic one, above all, it was not my own. That took like 3 days, but I did not post about it.

I am starting to scan the spi register right now, hopefully I will diagnose my problem.

Thanks a lot again!

edit: does bladeRF team allow me to copy the register map of the LMS and use it everytime as initialization?

[bpadalino]

No problem. Those commands were useful in debugging which is why they are in the CLI. I consider this a developer/enthusiast tool so most everything is configurable down to the register level.

As for the register map dump, sure - you can do whatever you want with it. It's your device, your configuration, your everything. Feel free to use it how you want.

Keep us informed if you need any other help or if you figure out your issue.