Hi!
I'm working on a stepped frequency radar using the bladerf 2.0 micro, and need to quickly retune 100-200 frequencies on both TX and RX using the schedule retuning functionality in libbladerf. So far I can retune each frequency with a constant period of 5.6ms using BLADERF_RETUNE_NOW, but with pre-scheduled retunes I am able to push the retuning period down to 0.6 ms (until the retuning buffer gets full).
As far as I could see from the Nios source code the maximum number of scheduled retunes are 16. At first I tried to wait for some of the scheduled retunes to pop from the buffer, and it works. However the rate at which retunes are scheduled is slower than the rate that they can be executed. This means that the code that schedules the retunes falls behind the actual retuning.
- Can I solve this without recompiling a custom FPGA build?
- If not: Is it possible to increase the retune buffer to say, 300?
- Is the buffer just specified in the Nios processor or in a VHDL buffer?
increasing FPGA retune size
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dritory
- Posts: 3
- Joined: Wed Sep 29, 2021 1:27 am
increasing FPGA retune size
Last edited by dritory on Tue Jan 14, 2025 7:21 am, edited 1 time in total.