Hi, I want to understand how does libbladerf and the sdr board work when using metadata and passing timestamps. Let's say i want to transmit data at time t0 and i pass the relevant parameters to the sync_tx function. Is the data transferred immediately to the fpga board and then sits there until the internal counter hits t0 and then at t0 the data is passed onto the dac, or does the library wait until time t0 and then starts transferring data to the fpga?
Are there buffers in the fpga that will hold these samples and then transmit is or is it done on the fly? What if i want to start sampling at a particular time?
SYNC_TX with METADATA
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ubiquitousacrobat
- Posts: 1
- Joined: Mon May 20, 2024 2:01 am
Re: SYNC_TX with METADATA
When you use the sync_tx function in libbladeRF and pass the relevant parameters, including a timestamp, here's how the process typically works:
Data Transfer to FPGA: The data is transferred from the host (your computer) to the FPGA on the bladeRF board immediately when you call the sync_tx function. This transfer fills the buffers within the FPGA.
Buffering in FPGA: The FPGA on the bladeRF has buffers that hold the samples. These buffers are part of the bladeRF's design to handle incoming data and manage timing. scratch geometry dash
Timestamp Handling: When you provide a timestamp, the FPGA’s internal counter (usually driven by a precise clock) is used to manage when the data should be transmitted. The data sits in the FPGA buffers until the internal counter matches the specified timestamp.
Transmission at t0: At the moment the internal counter hits the timestamp t0, the FPGA sends the buffered data to the DAC (Digital-to-Analog Converter) for transmission. This ensures that the transmission starts exactly at the specified time t0.
Data Transfer to FPGA: The data is transferred from the host (your computer) to the FPGA on the bladeRF board immediately when you call the sync_tx function. This transfer fills the buffers within the FPGA.
Buffering in FPGA: The FPGA on the bladeRF has buffers that hold the samples. These buffers are part of the bladeRF's design to handle incoming data and manage timing. scratch geometry dash
Timestamp Handling: When you provide a timestamp, the FPGA’s internal counter (usually driven by a precise clock) is used to manage when the data should be transmitted. The data sits in the FPGA buffers until the internal counter matches the specified timestamp.
Transmission at t0: At the moment the internal counter hits the timestamp t0, the FPGA sends the buffered data to the DAC (Digital-to-Analog Converter) for transmission. This ensures that the transmission starts exactly at the specified time t0.