bladeRF1.h

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#ifndef BLADERF1_H_
#define BLADERF1_H_
 
#define BLADERF_SAMPLERATE_MIN 80000u
 
#define BLADERF_SAMPLERATE_REC_MAX 40000000u
 
#define BLADERF_BANDWIDTH_MIN 1500000u
 
#define BLADERF_BANDWIDTH_MAX 28000000u
 
#define BLADERF_FREQUENCY_MIN_XB200 0u
 
#define BLADERF_FREQUENCY_MIN 237500000u
 
#define BLADERF_FREQUENCY_MAX 3800000000u
 
#define BLADERF_FLASH_ADDR_FIRMWARE 0x00000000
 
#define BLADERF_FLASH_BYTE_LEN_FIRMWARE 0x00030000
 
#define BLADERF_FLASH_ADDR_CAL 0x00030000
 
#define BLADERF_FLASH_BYTE_LEN_CAL 0x100
 
#define BLADERF_FLASH_ADDR_FPGA 0x00040000
 
#define BLADERF_RXVGA1_GAIN_MIN 5
 
#define BLADERF_RXVGA1_GAIN_MAX 30
 
#define BLADERF_RXVGA2_GAIN_MIN 0
 
#define BLADERF_RXVGA2_GAIN_MAX 30
 
#define BLADERF_TXVGA1_GAIN_MIN (-35)
 
#define BLADERF_TXVGA1_GAIN_MAX (-4)
 
#define BLADERF_TXVGA2_GAIN_MIN 0
 
#define BLADERF_TXVGA2_GAIN_MAX 25
 
typedef enum {
 BLADERF_LNA_GAIN_UNKNOWN, 
 BLADERF_LNA_GAIN_BYPASS, 
 BLADERF_LNA_GAIN_MID, 
 BLADERF_LNA_GAIN_MAX 
} bladerf_lna_gain;
 
#define BLADERF_LNA_GAIN_MID_DB 3
 
#define BLADERF_LNA_GAIN_MAX_DB 6
 
API_EXPORT
int CALL_CONV bladerf_set_txvga2(struct bladerf *dev, int gain);
 
API_EXPORT int CALL_CONV bladerf_get_txvga2(struct bladerf *dev, int *gain);
 
API_EXPORT
int CALL_CONV bladerf_set_txvga1(struct bladerf *dev, int gain);
 
API_EXPORT
int CALL_CONV bladerf_get_txvga1(struct bladerf *dev, int *gain);
 
API_EXPORT
int CALL_CONV bladerf_set_lna_gain(struct bladerf *dev, bladerf_lna_gain gain);
 
API_EXPORT
int CALL_CONV bladerf_get_lna_gain(struct bladerf *dev, bladerf_lna_gain *gain);
 
API_EXPORT
int CALL_CONV bladerf_set_rxvga1(struct bladerf *dev, int gain);
 
API_EXPORT
int CALL_CONV bladerf_get_rxvga1(struct bladerf *dev, int *gain);
 
API_EXPORT
int CALL_CONV bladerf_set_rxvga2(struct bladerf *dev, int gain);
 
API_EXPORT
int CALL_CONV bladerf_get_rxvga2(struct bladerf *dev, int *gain);
 
typedef enum {
 BLADERF_SAMPLING_UNKNOWN, 
 BLADERF_SAMPLING_INTERNAL, 
 BLADERF_SAMPLING_EXTERNAL 
} bladerf_sampling;
 
API_EXPORT
int CALL_CONV bladerf_set_sampling(struct bladerf *dev,
 bladerf_sampling sampling);
 
API_EXPORT
int CALL_CONV bladerf_get_sampling(struct bladerf *dev,
 bladerf_sampling *sampling);
 
 
typedef enum {
 BLADERF_LPF_NORMAL, 
 BLADERF_LPF_BYPASSED, 
 BLADERF_LPF_DISABLED 
} bladerf_lpf_mode;
 
API_EXPORT
int CALL_CONV bladerf_set_lpf_mode(struct bladerf *dev,
 bladerf_channel ch,
 bladerf_lpf_mode mode);
 
API_EXPORT
int CALL_CONV bladerf_get_lpf_mode(struct bladerf *dev,
 bladerf_channel ch,
 bladerf_lpf_mode *mode);
 
#define BLADERF_SMB_FREQUENCY_MAX 200000000u
 
#define BLADERF_SMB_FREQUENCY_MIN ((38400000u * 66u) / (32 * 567))
 
 
typedef enum {
 BLADERF_SMB_MODE_INVALID = -1, 
 BLADERF_SMB_MODE_DISABLED, 
 BLADERF_SMB_MODE_OUTPUT, 
 BLADERF_SMB_MODE_INPUT, 
 BLADERF_SMB_MODE_UNAVAILBLE, 
} bladerf_smb_mode;
 
API_EXPORT
int CALL_CONV bladerf_set_smb_mode(struct bladerf *dev, bladerf_smb_mode mode);
 
API_EXPORT
int CALL_CONV bladerf_get_smb_mode(struct bladerf *dev, bladerf_smb_mode *mode);
 
API_EXPORT
int CALL_CONV
 bladerf_set_rational_smb_frequency(struct bladerf *dev,
 struct bladerf_rational_rate *rate,
 struct bladerf_rational_rate *actual);
 
API_EXPORT
int CALL_CONV bladerf_set_smb_frequency(struct bladerf *dev,
 uint32_t rate,
 uint32_t *actual);
 
API_EXPORT
int CALL_CONV bladerf_get_rational_smb_frequency(
 struct bladerf *dev, struct bladerf_rational_rate *rate);
 
API_EXPORT
int CALL_CONV bladerf_get_smb_frequency(struct bladerf *dev,
 unsigned int *rate);
 
#define BLADERF_XB_GPIO(n) (1 << (n - 1))
 
#define BLADERF_XB_DIR_OUTPUT(pin) (pin)
 
#define BLADERF_XB_DIR_INPUT(pin) (0)
 
#define BLADERF_XB_GPIO_01 BLADERF_XB_GPIO(1)
 
#define BLADERF_XB_GPIO_02 BLADERF_XB_GPIO(2)
 
#define BLADERF_XB_GPIO_03 BLADERF_XB_GPIO(3)
 
#define BLADERF_XB_GPIO_04 BLADERF_XB_GPIO(4)
 
#define BLADERF_XB_GPIO_05 BLADERF_XB_GPIO(5)
 
#define BLADERF_XB_GPIO_06 BLADERF_XB_GPIO(6)
 
#define BLADERF_XB_GPIO_07 BLADERF_XB_GPIO(7)
 
#define BLADERF_XB_GPIO_08 BLADERF_XB_GPIO(8)
 
#define BLADERF_XB_GPIO_09 BLADERF_XB_GPIO(9)
 
#define BLADERF_XB_GPIO_10 BLADERF_XB_GPIO(10)
 
#define BLADERF_XB_GPIO_11 BLADERF_XB_GPIO(11)
 
#define BLADERF_XB_GPIO_12 BLADERF_XB_GPIO(12)
 
#define BLADERF_XB_GPIO_13 BLADERF_XB_GPIO(13)
 
#define BLADERF_XB_GPIO_14 BLADERF_XB_GPIO(14)
 
#define BLADERF_XB_GPIO_15 BLADERF_XB_GPIO(15)
 
#define BLADERF_XB_GPIO_16 BLADERF_XB_GPIO(16)
 
#define BLADERF_XB_GPIO_17 BLADERF_XB_GPIO(17)
 
#define BLADERF_XB_GPIO_18 BLADERF_XB_GPIO(18)
 
#define BLADERF_XB_GPIO_19 BLADERF_XB_GPIO(19)
 
#define BLADERF_XB_GPIO_20 BLADERF_XB_GPIO(20)
 
#define BLADERF_XB_GPIO_21 BLADERF_XB_GPIO(21)
 
#define BLADERF_XB_GPIO_22 BLADERF_XB_GPIO(22)
 
#define BLADERF_XB_GPIO_23 BLADERF_XB_GPIO(23)
 
#define BLADERF_XB_GPIO_24 BLADERF_XB_GPIO(24)
 
#define BLADERF_XB_GPIO_25 BLADERF_XB_GPIO(25)
 
#define BLADERF_XB_GPIO_26 BLADERF_XB_GPIO(26)
 
#define BLADERF_XB_GPIO_27 BLADERF_XB_GPIO(27)
 
#define BLADERF_XB_GPIO_28 BLADERF_XB_GPIO(28)
 
#define BLADERF_XB_GPIO_29 BLADERF_XB_GPIO(29)
 
#define BLADERF_XB_GPIO_30 BLADERF_XB_GPIO(30)
 
#define BLADERF_XB_GPIO_31 BLADERF_XB_GPIO(31)
 
#define BLADERF_XB_GPIO_32 BLADERF_XB_GPIO(32)
 
 
#define BLADERF_XB200_PIN_J7_1 BLADERF_XB_GPIO_10
 
#define BLADERF_XB200_PIN_J7_2 BLADERF_XB_GPIO_11
 
#define BLADERF_XB200_PIN_J7_5 BLADERF_XB_GPIO_08
 
#define BLADERF_XB200_PIN_J7_6 BLADERF_XB_GPIO_09
 
#define BLADERF_XB200_PIN_J13_1 BLADERF_XB_GPIO_17
 
#define BLADERF_XB200_PIN_J13_2 BLADERF_XB_GPIO_18
 
/* XB-200 J13 Pin 6 is actually reserved for SPI */
 
#define BLADERF_XB200_PIN_J16_1 BLADERF_XB_GPIO_31
 
#define BLADERF_XB200_PIN_J16_2 BLADERF_XB_GPIO_32
 
#define BLADERF_XB200_PIN_J16_3 BLADERF_XB_GPIO_19
 
#define BLADERF_XB200_PIN_J16_4 BLADERF_XB_GPIO_20
 
#define BLADERF_XB200_PIN_J16_5 BLADERF_XB_GPIO_21
 
#define BLADERF_XB200_PIN_J16_6 BLADERF_XB_GPIO_24
 
#define BLADERF_XB100_PIN_J2_3 BLADERF_XB_GPIO_07
 
#define BLADERF_XB100_PIN_J2_4 BLADERF_XB_GPIO_08
 
#define BLADERF_XB100_PIN_J3_3 BLADERF_XB_GPIO_09
 
#define BLADERF_XB100_PIN_J3_4 BLADERF_XB_GPIO_10
 
#define BLADERF_XB100_PIN_J4_3 BLADERF_XB_GPIO_11
 
#define BLADERF_XB100_PIN_J4_4 BLADERF_XB_GPIO_12
 
#define BLADERF_XB100_PIN_J5_3 BLADERF_XB_GPIO_13
 
#define BLADERF_XB100_PIN_J5_4 BLADERF_XB_GPIO_14
 
#define BLADERF_XB100_PIN_J11_2 BLADERF_XB_GPIO_05
 
#define BLADERF_XB100_PIN_J11_3 BLADERF_XB_GPIO_04
 
#define BLADERF_XB100_PIN_J11_4 BLADERF_XB_GPIO_03
 
#define BLADERF_XB100_PIN_J11_5 BLADERF_XB_GPIO_06
 
#define BLADERF_XB100_PIN_J12_2 BLADERF_XB_GPIO_01
 
/* XB-100 header J12, pins 3 and 4 are reserved for SPI */
 
#define BLADERF_XB100_PIN_J12_5 BLADERF_XB_GPIO_02
 
#define BLADERF_XB100_LED_D1 BLADERF_XB_GPIO_24
 
#define BLADERF_XB100_LED_D2 BLADERF_XB_GPIO_32
 
#define BLADERF_XB100_LED_D3 BLADERF_XB_GPIO_30
 
#define BLADERF_XB100_LED_D4 BLADERF_XB_GPIO_28
 
#define BLADERF_XB100_LED_D5 BLADERF_XB_GPIO_23
 
#define BLADERF_XB100_LED_D6 BLADERF_XB_GPIO_25
 
#define BLADERF_XB100_LED_D7 BLADERF_XB_GPIO_31
 
#define BLADERF_XB100_LED_D8 BLADERF_XB_GPIO_29
 
#define BLADERF_XB100_TLED_RED BLADERF_XB_GPIO_22
 
#define BLADERF_XB100_TLED_GREEN BLADERF_XB_GPIO_21
 
#define BLADERF_XB100_TLED_BLUE BLADERF_XB_GPIO_20
 
#define BLADERF_XB100_DIP_SW1 BLADERF_XB_GPIO_27
 
#define BLADERF_XB100_DIP_SW2 BLADERF_XB_GPIO_26
 
#define BLADERF_XB100_DIP_SW3 BLADERF_XB_GPIO_16
 
#define BLADERF_XB100_DIP_SW4 BLADERF_XB_GPIO_15
 
#define BLADERF_XB100_BTN_J6 BLADERF_XB_GPIO_19
 
#define BLADERF_XB100_BTN_J7 BLADERF_XB_GPIO_18
 
#define BLADERF_XB100_BTN_J8 BLADERF_XB_GPIO_17
 
/* XB-100 buttons J9 and J10 are not mapped to the GPIO register,
 * but instead to reserved SPI pins. FPGA modifications are needed to
 * use these. */
 
API_EXPORT
int CALL_CONV bladerf_expansion_gpio_read(struct bladerf *dev, uint32_t *val);
 
API_EXPORT
int CALL_CONV bladerf_expansion_gpio_write(struct bladerf *dev, uint32_t val);
 
API_EXPORT
int CALL_CONV bladerf_expansion_gpio_masked_write(struct bladerf *dev,
 uint32_t mask,
 uint32_t value);
 
API_EXPORT
int CALL_CONV bladerf_expansion_gpio_dir_read(struct bladerf *dev,
 uint32_t *outputs);
 
API_EXPORT
int CALL_CONV bladerf_expansion_gpio_dir_write(struct bladerf *dev,
 uint32_t outputs);
 
API_EXPORT
int CALL_CONV bladerf_expansion_gpio_dir_masked_write(struct bladerf *dev,
 uint32_t mask,
 uint32_t outputs);
 
typedef enum {
 BLADERF_XB200_50M = 0,
 
 BLADERF_XB200_144M,
 
 BLADERF_XB200_222M,
 
 BLADERF_XB200_CUSTOM,
 
 BLADERF_XB200_AUTO_1DB,
 
 BLADERF_XB200_AUTO_3DB
} bladerf_xb200_filter;
 
typedef enum {
 BLADERF_XB200_BYPASS = 0, 
 BLADERF_XB200_MIX 
} bladerf_xb200_path;
 
typedef enum {
 BLADERF_XB300_TRX_INVAL = -1, 
 BLADERF_XB300_TRX_TX = 0, 
 BLADERF_XB300_TRX_RX, 
 BLADERF_XB300_TRX_UNSET 
} bladerf_xb300_trx;
 
typedef enum {
 BLADERF_XB300_AMP_INVAL = -1, 
 BLADERF_XB300_AMP_PA = 0, 
 BLADERF_XB300_AMP_LNA, 
 BLADERF_XB300_AMP_PA_AUX 
} bladerf_xb300_amplifier;
 
API_EXPORT
int CALL_CONV bladerf_xb200_set_filterbank(struct bladerf *dev,
 bladerf_channel ch,
 bladerf_xb200_filter filter);
 
API_EXPORT
int CALL_CONV bladerf_xb200_get_filterbank(struct bladerf *dev,
 bladerf_channel ch,
 bladerf_xb200_filter *filter);
 
API_EXPORT
int CALL_CONV bladerf_xb200_set_path(struct bladerf *dev,
 bladerf_channel ch,
 bladerf_xb200_path path);
 
API_EXPORT
int CALL_CONV bladerf_xb200_get_path(struct bladerf *dev,
 bladerf_channel ch,
 bladerf_xb200_path *path);
 
API_EXPORT
int CALL_CONV bladerf_xb300_set_trx(struct bladerf *dev, bladerf_xb300_trx trx);
 
API_EXPORT
int CALL_CONV bladerf_xb300_get_trx(struct bladerf *dev,
 bladerf_xb300_trx *trx);
 
API_EXPORT
int CALL_CONV bladerf_xb300_set_amplifier_enable(struct bladerf *dev,
 bladerf_xb300_amplifier amp,
 bool enable);
API_EXPORT
int CALL_CONV bladerf_xb300_get_amplifier_enable(struct bladerf *dev,
 bladerf_xb300_amplifier amp,
 bool *enable);
API_EXPORT
int CALL_CONV bladerf_xb300_get_output_power(struct bladerf *dev, float *val);
 
typedef enum {
 BLADERF_DC_CAL_INVALID = -1,
 BLADERF_DC_CAL_LPF_TUNING,
 BLADERF_DC_CAL_TX_LPF,
 BLADERF_DC_CAL_RX_LPF,
 BLADERF_DC_CAL_RXVGA2
} bladerf_cal_module;
 
API_EXPORT
int CALL_CONV bladerf_calibrate_dc(struct bladerf *dev,
 bladerf_cal_module module);
 
#define BLADERF_GPIO_LMS_RX_ENABLE (1 << 1)
 
#define BLADERF_GPIO_LMS_TX_ENABLE (1 << 2)
 
#define BLADERF_GPIO_TX_LB_ENABLE (2 << 3)
 
#define BLADERF_GPIO_TX_HB_ENABLE (1 << 3)
 
#define BLADERF_GPIO_COUNTER_ENABLE (1 << 9)
 
#define BLADERF_GPIO_RX_MUX_MASK (0x7 << BLADERF_GPIO_RX_MUX_SHIFT)
 
#define BLADERF_GPIO_RX_MUX_SHIFT 8
 
#define BLADERF_GPIO_RX_LB_ENABLE (2 << 5)
 
#define BLADERF_GPIO_RX_HB_ENABLE (1 << 5)
 
#define BLADERF_GPIO_FEATURE_SMALL_DMA_XFER (1 << 7)
 
#define BLADERF_GPIO_PACKET (1 << 19)
 
#define BLADERF_GPIO_8BIT_MODE (1 << 20)
 
#define BLADERF_GPIO_AGC_ENABLE (1 << 18)
 
#define BLADERF_GPIO_TIMESTAMP (1 << 16)
 
#define BLADERF_GPIO_TIMESTAMP_DIV2 (1 << 17)
 
#define BLADERF_GPIO_PACKET_CORE_PRESENT (1 << 28)
 
API_EXPORT
int CALL_CONV bladerf_dac_write(struct bladerf *dev, uint16_t val);
 
API_EXPORT
int CALL_CONV bladerf_dac_read(struct bladerf *dev, uint16_t *val);
 
API_EXPORT
int CALL_CONV bladerf_si5338_read(struct bladerf *dev,
 uint8_t address,
 uint8_t *val);
 
API_EXPORT
int CALL_CONV bladerf_si5338_write(struct bladerf *dev,
 uint8_t address,
 uint8_t val);
 
API_EXPORT
int CALL_CONV bladerf_lms_read(struct bladerf *dev,
 uint8_t address,
 uint8_t *val);
 
API_EXPORT
int CALL_CONV bladerf_lms_write(struct bladerf *dev,
 uint8_t address,
 uint8_t val);
 
struct bladerf_lms_dc_cals {
 int16_t lpf_tuning; 
 int16_t tx_lpf_i; 
 int16_t tx_lpf_q; 
 int16_t rx_lpf_i; 
 int16_t rx_lpf_q; 
 int16_t dc_ref; 
 int16_t rxvga2a_i; 
 int16_t rxvga2a_q; 
 int16_t rxvga2b_i; 
 int16_t rxvga2b_q; 
};
 
API_EXPORT
int CALL_CONV bladerf_lms_set_dc_cals(
 struct bladerf *dev, const struct bladerf_lms_dc_cals *dc_cals);
 
API_EXPORT
int CALL_CONV bladerf_lms_get_dc_cals(struct bladerf *dev,
 struct bladerf_lms_dc_cals *dc_cals);
 
API_EXPORT
int CALL_CONV bladerf_xb_spi_write(struct bladerf *dev, uint32_t val);
 
#endif /* BLADERF1_H_ */