Digital backloop
Posted: Thu Oct 13, 2016 5:19 am
Hello,
I searched all over for an answer to my question but could not find any.
I would like to use bladeRF as an effective frequency translation device, meaning I would like the FPGA to pipe in the DAC whatever it has received from the ADC.
The LMS normally supports independent frequencies for RX and TX so that the signal received in RX is broadcast with no change on TX but at either lower or higher frequency.
I have seen lots of possible loop-back modes, but are currently any back-loop modes enabled (RX->TX)?
Cheers,
Mic
I searched all over for an answer to my question but could not find any.
I would like to use bladeRF as an effective frequency translation device, meaning I would like the FPGA to pipe in the DAC whatever it has received from the ADC.
The LMS normally supports independent frequencies for RX and TX so that the signal received in RX is broadcast with no change on TX but at either lower or higher frequency.
I have seen lots of possible loop-back modes, but are currently any back-loop modes enabled (RX->TX)?
Cheers,
Mic