Official bladeRF forum

Couple questions if / when anyone has a few minutes. First is there a way to have the build script generate symbol files? I work better visually. I can manually select each file to build the symbol but thats time consuming.

I've also had problems compiling anything other than the hosted rev. Different errors depending on what rev but for headless I believe it was missing architecture line 27.

This is for the 40k chip and I'm using Quartus 13.1.4 with the cygwin patch from altera.

Thanks in adv

Tom

The current supported FPGA images are the hosted and atsc_tx. The others have suffered bitrot and are not really used.

If you want to build up the headless one, there needs to be come work done to get the lms.c and si5338.c control files back into the NIOS code build. Moreover, you'll need a way to actually do something autonomous with them.

If you want a visualization, after you make the Quartus II project, you can go into the Quartus II GUI and look at the RTL view of the design. That is the basic block diagram of what the HDL is doing.

Hope this helpful.

Brian