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Posted: **Tue Apr 01, 2014 9:42 am**

I am having trouble getting ModelSim up and running to support some HDL work that I have been doing. It is likely the result of operator error -- I used ModelSim for some Xilinx based projects a few years ago so I have some familiarity, but am brand new the the Altera/Quartus environment and am definitely rusty when it comes to the process so I appreciate your patience.

For starters, I am getting an error when running ModelSim on a clean bladeRF project (hosted, 115KLE). After cloning, building, and opening the project in Quartus, I run the RTL Simulator and see the following log output once ModelSim launches:

Code: Select all

// other stuff
# -- Compiling architecture hosted_bladerf of bladerf
# ++ Error: (vcom-11) Could not find work.bladerf
# ++ Error: ~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd(27): VHDL Compiler exiting
# ++ Error: ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.
# Error in macro ./hosted_run_msim_rtl_vhdl.do line 68
# ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.
#       while executing
# "vcom -2008 -work work {~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd}"

ModelSim>

As I mentioned this is on a stock project, so I suspect it could be a configuration or path problem. I know the *_tb.vhd and *.vho files are spread out throughout the project tree, so is there a certain directory I should be in when doing this? Once I get up and running with these stock bladeRF testbenches I can apply that configuration to my own application. Please let me know if I can provide any additional information. Thanks!

Posted: **Tue Apr 01, 2014 9:46 am**

Also, if there are best practices that pertain to developing and testing for the BladeRF FPGA I would appreciate any and all guidance. Thanks!

Posted: **Tue Apr 01, 2014 10:05 am**

Hi postman,

What OS are you using?

I'm not familiar with HDL work, but I found an interesting blog of someone who was able to compile a simple blinking LED HDL and details how he did it in Windows. I was able to do the same, following his recipe:

http://bladerf.blogspot.com/2014/02/bla ... artus.html
http://bladerf.blogspot.com/2014/02/fin ... h-new.html

I'd imagine you can follow a similar process on Linux. You've probably found this link already:

https://github.com/Nuand/bladeRF/tree/master/hdl

Hope it helps

Posted: **Tue Apr 01, 2014 10:54 am**

Thanks for the blog link mponce, I hadn't seen that before. Unfortunately the author does not delve into testbenches, which are what I am interested in. Testbenches are scripts that enable verification and simulation of an HDL design -- he went through how to modify the HDL and produce a binary, but not how to test it using the simulation tools. I am on Ubuntu 13.10 for reference.

The references that I have found on the forums and in the BladeRF documentation have been to the effect of "Use testbenches, they're really awesome!" without going into detail. If anyone can point me in the right direction I would be happy to write up a description of the full process for the docs once I am successful.

Posted: **Sun May 04, 2014 6:37 am**

I did the Altera tutorial and after that I was able to write a simple testbench myself.
I did my best to show every step I did in the hope that you will see how easy this all is.
OK, I am a newby in testbenches but I will try to set up something serious after all.
In the meantime I will show how I did it and talk out loudly what and why I am doing, inclusive all my errors because other's errors are good for learning (and for entertainment perhaps..). I still say: ModelSim is awesome!
My blog is at http://bladerf.blogspot.nl/
Feel free to comment, I enjoy this whole process around bladeRF very much.
Regards,
Kees

Posted: **Mon May 05, 2014 12:18 am**

I have looked at your tutorial and I have some comments.

First of all, your testbench should not have any ports because its aim is only to generate stimulus for your DUT, you just have to let the entity empty.

Then, a good practice for describing an hardware block which uses registers is to clearly define a flip-flop (FF - basic element of a register). The advantage is that the synthesis tool will well understand what you want to do and thus the result will be better. A FF has an input (D) which is transferred to the output (Q) when a clock edge is detected. The output can be cleared when a reset signal is detected. So, I would have made the 5-bits counter like that:

Code: Select all

signal counter_d, counter_q	:	std_logic_vector(4 down to 0);

COUNTER_reg:process(clk, reset)
begin
	if reset = ‘0’ then
		counter_q <= (others => ‘0’);
	else
		if clk’event and clk = ‘1’
			counter_q <= std_logic_vector(unsigned(counter_d) + 1); 
		else
			counter_q <= counter_d;
		end if;
	end if;
end process;

For doing arithmetic operations such as an addition on a std_logic_vector you have to convert it in an unsigned/signed and then back to an std_logic_vector. Actually, signed/unsigned are std_logic_vector which are understood as numeric values, so you can define the counter_d/_q signals directly as unsigned. After all, when you synthesizes this design, you will have a 5-bits register with a multiplexer on the input which selects between the increment input (counter + 1) and the memory input (output connected to the input) depending on the clock signal.

I encourage you to think hardware, so to describe what you want to do with logic gates and circuits. Your counter description is more like a software. For checking the result of the synthesis, try to watch in Quartus the schematic of your design. If you need any help don't hesitate to ask your questions on the forum !

PS : vcom is the command for compiling the code. The working library has to be defined with the -work option and here it does not correspond to the good one. Thus, you do not have to put all your source files in the work folder, just precise the working library. If you want to create a new work library, use the vlib command.

Code: Select all

// other stuff
# -- Compiling architecture hosted_bladerf of bladerf
# ++ Error: (vcom-11) Could not find work.bladerf
# ++ Error: ~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd(27): VHDL Compiler exiting
# ++ Error: ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.
# Error in macro ./hosted_run_msim_rtl_vhdl.do line 68
# ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.
#       while executing
# "vcom -2008 -work work {~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd}"

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