I have looked at your tutorial and I have some comments.
First of all, your testbench should not have any ports because its aim is only to generate stimulus for your DUT, you just have to let the entity empty.
Then, a good practice for describing an hardware block which uses registers is to clearly define a flip-flop (FF - basic element of a register). The advantage is that the synthesis tool will well understand what you want to do and thus the result will be better. A FF has an input (D) which is transferred to the output (Q) when a clock edge is detected. The output can be cleared when a reset signal is detected. So, I would have made the 5-bits counter like that:
Code: Select all
signal counter_d, counter_q : std_logic_vector(4 down to 0);
COUNTER_reg:process(clk, reset)
begin
if reset = ‘0’ then
counter_q <= (others => ‘0’);
else
if clk’event and clk = ‘1’
counter_q <= std_logic_vector(unsigned(counter_d) + 1);
else
counter_q <= counter_d;
end if;
end if;
end process;
For doing arithmetic operations such as an addition on a std_logic_vector you have to convert it in an unsigned/signed and then back to an std_logic_vector. Actually, signed/unsigned are std_logic_vector which are understood as numeric values, so you can define the counter_d/_q signals directly as unsigned. After all, when you synthesizes this design, you will have a 5-bits register with a multiplexer on the input which selects between the increment input (counter + 1) and the memory input (output connected to the input) depending on the clock signal.
I encourage you to think hardware, so to describe what you want to do with logic gates and circuits. Your counter description is more like a software. For checking the result of the synthesis, try to watch in Quartus the schematic of your design. If you need any help don't hesitate to ask your questions on the forum !
PS : vcom is the command for compiling the code. The working library has to be defined with the -work option and here it does not correspond to the good one. Thus, you do not have to put all your source files in the work folder, just precise the working library. If you want to create a new work library, use the vlib command.
Code: Select all
// other stuff
# -- Compiling architecture hosted_bladerf of bladerf
# ++ Error: (vcom-11) Could not find work.bladerf
# ++ Error: ~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd(27): VHDL Compiler exiting
# ++ Error: ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.
# Error in macro ./hosted_run_msim_rtl_vhdl.do line 68
# ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.
# while executing
# "vcom -2008 -work work {~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd}"
ModelSim>