The GPIF doesn't actually control DMA_RX (or even DMA_TX), they are in fact reclaimed as GPIO for the FX3 by NuandGPIOReconfigure(). These GPIOs are controlled by USB request handlers (
https://github.com/Nuand/bladeRF/blob/m ... eRF.c#L859 ).
Your analysis is right, the cyfx file does not match the FPGA's expectation.
So, according to the GPIF designer DMA_RX is CTL[4] (GPIO[21]).
bladerf.h defines GPIO_RX_EN as GPIO pin 21.
#define GPIO_RX_EN 21
And the HDL defined CTL[4] as dma_rx_en
dma_rx_en <= fx3_ctl(4);
DMA_TX according to the GPIF designer is CTL[9] (GPIO[26]), there is a discrepancy with how the FX3 firmware controls DMA_TX here. According to bladerf.h:
#define GPIO_TX_EN 22
GPIO[33] is actually CTL[5], which matches with the HDL declaration for dma_tx_en:
dma_tx_en <= fx3_ctl(5);
Since it is the FX3 source code that controls the RX and TX pins, you should ignore the GPIF designer, and concentrate on what you see in the fx3 firmware. This discrepancy ought to be corrected, thanks for pointing it out.
Lastly, DMA_DONE is defined as CTL[10] (GPIO[27]) in the GPIF designer, and this pin is actually controlled by the GPIF. So in this case this is a discrepancy that would affect the GPIF's operation.
It appears as if the .cyfx file has a previous version of the RFLink interface, yet the resulting "cyfxgpif_RFlink.h" file has the latest interface changes. This basically means the FX3 is running the latest interface code, however the project file that created it wasn't saved. We will clean up the GPIF Designer project file to make it match the latest GPIF interface.