FPGA: Pipe Rx samples to Tx
Posted: Tue Nov 28, 2023 11:45 am
Hello!
Has anyone tried modifying the VHDL code in order to pipe received IQ samples off the rx_fifo into the tx_fifo?
What I am trying to accomplish is setup the bladeRF as a headless transponder.
Has anyone tried modifying the VHDL code in order to pipe received IQ samples off the rx_fifo into the tx_fifo?
What I am trying to accomplish is setup the bladeRF as a headless transponder.