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FPGA: Pipe Rx samples to Tx

Posted: Tue Nov 28, 2023 11:45 am
by seanybooboo
Hello!

Has anyone tried modifying the VHDL code in order to pipe received IQ samples off the rx_fifo into the tx_fifo?

What I am trying to accomplish is setup the bladeRF as a headless transponder.

Re: FPGA: Pipe Rx samples to Tx

Posted: Thu Dec 07, 2023 2:57 am
by dariusbotha
Hello,

that should not be too difficult. Have a look at piping the data between the fifo_reader (Tx) and fifo_writer (Rx).