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Hello,

I attempted to utilize the BladeRF SDR for signal power measurement. My approach involved connecting the signal generator directly to BladeRF's RX 1, using a sinusoidal wave at 400 MHz with a power level of -35 dBm. MATLAB was employed to control the SDR, and the signal power was calculated using the formula: rms(x)^2. After 1 hour of measurement, a significant deviation was observed between the final and initial measurement results (refer to Figure 1, Iteration number: 1 iteration is equivalent to 2s ). Figure 2 illustrates the temperature readings from the internal temperature sensor of the SDR.

After approximately 1 hour of measurement, I incrementally increased the input power levels from the signal generator to -25 dBm and -20 dBm, respectively. The deviation exhibited a linear increase corresponding to the rise in input power.

My inquiry is as follows: Is this deviation normal, and what could be the reason for the substantial deviation attributed to heating effect

Please note: the AGC was set to manual mode and the gain was always 0 dB at Rx1.

Thank you.

Figure 1:


Figure 2:

This was resolved via email. For posterity's sake: it appears having a CW on top of or way too close to the LO causes the AD9361's builtin DC offset calibration to try to remove the over the air signal. The solution is to move the CW away from the LO.

robert.ghilduta wrote: ↑Tue Jan 09, 2024 4:04 am This was resolved via email. For posterity's sake: it appears having a CW on top of or way too close to the LO causes the AD9361's builtin DC offset calibration to try to remove the over the air signal. The solution is to move the CW away from the LO. drift boss

That can solve how long it takes to maintain

Okay, managed to solve this by manual uploading of the FPGA from python and not installing the auto FPGA loader.

Although you mentioned that the AGC was set to manual mode and the gain was fixed at 0 dB drift hunters it's worth double-checking that there are no unintended changes in gain or AGC behavior during the measurement. Automatic gain control can introduce variations if not properly controlled.

tynsaras wrote: ↑Thu Feb 01, 2024 12:55 am doodle jump
Okay, managed to solve this by manual uploading of the FPGA from python and not installing the auto FPGA loader.

Is there another easier way?

robert.ghilduta wrote: ↑Tue Jan 09, 2024 4:04 am This was resolved via emailbasketbros. For posterity's sake: it appears having a CW on top of or way too close to the LO causes the AD9361's builtin DC offset calibration to try to remove the over the air signal. The solution is to move the CW away from the LO.

Je recherche également des informations sur ce problème. C'était une coïncidence de voir ton commentaire.