Hi there,
I have got access to a splendid bladeRF device, and inclined to do some FPGA works.
My current goal is to create a standalone RF impairment simulator in AWGN and Rayleigh fading channels.
Since my application is headless, the simulation and testing is essential to implement it successfully.
I wrote some signal processing units and unit-tested them using ModelSim, and then I integrated them into a signal processing chain.
Before deploying the whole design to the device, I'd like to the top-level simulation and verify my design works fine.
I checked the repository and found there seems to be a way to simulate the integrated signal processing chain.
https://github.com/Nuand/bladeRF/commit ... 863874b4f8
However, I cannot understand how to do this because of my little experience on FPGA design.
Could you tell me how to do the top-level simulation, or is there a more efficient way to test the integrated design?
Best regards,
Kaito
Top-level Simulaition Using ModelSim?
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- Posts: 6
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Re: Top-level Simulaition Using ModelSim?
There are no replies to this, is it because it hasn't been done yet? I'm also looking to simulate FPGA development. A little bit of help in getting started with modelSim would be awesome. I see some things in the FPGA directories that makes it look like it has been set up for modelSim.
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- Posts: 201
- Joined: Thu Jun 18, 2015 6:10 pm
Re: Top-level Simulaition Using ModelSim?
We use ModelSim-Altera, which can be installed as part of the Altera Quartus package. There are a number of tutorials online on how to get started with ModelSim, so I'm not going to get into it too much here. If you have any specific questions about simulating a bladeRF design, or you run into problems (something doesn't compile, etc.), I'll do my best to try to answer them. All of this can be scripted, but the general GUI flow is as follows:
If you don't have one already, I highly recommend getting a Terasic USB Blaster so you can use SignalTap to debug the FPGA design in hardware. It really is an invaluable debugging tool, especially for those edge cases you may not have considered in simulation!
- - Open up ModelSim from within the modelsim directory of the bladeRF platform
- Run the compile.do script by typing "do compile.do" in the ModelSim console (transcript window).- This will compile all the dependent files into the appropriate libraries and elaborate the design.
- Run the simulation; "run 500 us" will simulate 500 microseconds of time. You may need more or less depending on what you're trying to evaluate.
If you don't have one already, I highly recommend getting a Terasic USB Blaster so you can use SignalTap to debug the FPGA design in hardware. It really is an invaluable debugging tool, especially for those edge cases you may not have considered in simulation!
Electrical Engineer
Nuand, LLC.
Nuand, LLC.
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- Posts: 6
- Joined: Thu Jan 26, 2017 12:46 pm
Re: Top-level Simulaition Using ModelSim?
Awesome, thank you!
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- Posts: 11
- Joined: Mon Apr 11, 2016 12:41 pm
Re: Top-level Simulaition Using ModelSim?
I'd just like to add that some files need to be tweaked before the compile.do script actually compiles the code without errors. Specifically, nuand.do and nios_system.vhd are missing a few lines of code:
1) Add the following to the end of the entity declaration in hdl/fpga/ip/altera/nios_system/simulation/nios_system.vhd.
Don't forget to also place a semicolon at the end of the line with the "xb_gpio_dir_export" port declaration.
2) Replace hdl/fpga/ip/nuand/nuand.do with the following (I added the missing modules)
Maybe I can put these changes in a pull request soon. I think they were just forgotten in the last update.
1) Add the following to the end of the entity declaration in hdl/fpga/ip/altera/nios_system/simulation/nios_system.vhd.
Code: Select all
vctcxo_tamer_tune_ref : in std_logic;
vctcxo_tamer_vctcxo_clock : in std_logic;
tx_trigger_ctl_in_port : in std_logic_vector(7 downto 0);
tx_trigger_ctl_out_port : out std_logic_vector(7 downto 0);
rx_trigger_ctl_in_port : in std_logic_vector(7 downto 0);
rx_trigger_ctl_out_port : out std_logic_vector(7 downto 0)
2) Replace hdl/fpga/ip/nuand/nuand.do with the following (I added the missing modules)
Code: Select all
proc compile_nuand { root } {
vlib nuand
vcom -work nuand -2008 [file join $root ../altera/tx_fifo/tx_fifo.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/constellation_mapper.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/sync_fifo.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/uart.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/cordic.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/nco.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/fsk_modulator.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/fsk_demodulator.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/uart.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/tan_table.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/iq_correction.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/synchronizer.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/reset_synchronizer.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/handshake.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/tb/handshake_tb.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/signal_processing_p.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/bit_stripper.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/fir_filter.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/atsc_tx.vhd]
vcom -work nuand -2008 [file join $root ./simulation/util.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/tb/fir_filter_tb.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/tb/atsc_tx_tb.vhd]
vcom -work nuand -2008 [file join $root ./simulation/fx3_model.vhd]
vcom -work nuand -2008 [file join $root ./simulation/lms6002d_model.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/lms6002d/vhdl/lms6002d.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/lms6002d/vhdl/tb/lms6002d_tb.vhd]
vcom -work nuand -2008 [file join $root ../altera/rx_fifo/rx_fifo.vhd]
vcom -work nuand -2008 [file join $root ../altera/tx_fifo/tx_fifo.vhd]
vcom -work nuand -2008 [file join $root ../altera/rx_meta_fifo/rx_meta_fifo.vhd]
vcom -work nuand -2008 [file join $root ../altera/tx_meta_fifo/tx_meta_fifo.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/fifo_reader.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/fifo_writer.vhd]
vcom -work nuand -2008 [file join $root ./simulation/sample_stream_tb.vhd]
vcom -work nuand -2008 [file join $root ./trigger/trigger.vhd]
vcom -work nuand -2008 [file join $root ./synthesis/signal_generator.vhd]
}
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- Posts: 201
- Joined: Thu Jun 18, 2015 6:10 pm
Re: Top-level Simulaition Using ModelSim?
Good catch, ifrasch, thanks. Feel free to submit the PR at your convenience and we'll pull it in.
Electrical Engineer
Nuand, LLC.
Nuand, LLC.
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- Posts: 6
- Joined: Thu Jan 26, 2017 12:46 pm
Re: Top-level Simulaition Using ModelSim?
Quick update: I am now able to simulate just simple testbenches in ModelSim that I've started through the blade_rf project. What I do is this:
- put all my custom code into a module (that is inserted into the bladerf top level)
- create a testbench for that module
- launch modelsim from Quartus (this runs all necessary scripts and includes files needed to simulate with Altera IP)
- run simulations in ModelSim
So I am still not simulating the entire bladerf but I think it's enough for what I'm trying to accomplish.
Chris
- put all my custom code into a module (that is inserted into the bladerf top level)
- create a testbench for that module
- launch modelsim from Quartus (this runs all necessary scripts and includes files needed to simulate with Altera IP)
- run simulations in ModelSim
So I am still not simulating the entire bladerf but I think it's enough for what I'm trying to accomplish.
Chris