The "Calibrate" Command and a few other ??'s

[scancapecod]

Hello,

Due to some alias and image problems I had been experiencing (and still am) it was suggested to me in another thread that I try to calibrate the bladeRF using the "calibrate" command at the cli prompt, which I have done. I'm still trying to puzzle out if it is helping. But my question is pertinent to warning messages I receive when running calibrate at the command line, as shown below:

bladeRF> calibrate
[WARNING] Never converged - DC_CLBR_DONE: 1 DC_LOCK: 0
[WARNING] Never converged - DC_CLBR_DONE: 1 DC_LOCK: 0

Can someone provide an explanation of exactly what this means? Also, are there any other commands that may further assist with reducing imaging and aliasing? I see a "correct" option but I'm not sure what "arguments" to provide, or if it would even help; it is pertinent to IQ imbalances.

Finally, is there a "for dummies" in depth explanation of these commands available anywhere, and also for the various commands available to me via SDRConsole to include VGA1, VGA2, LPF, and LNA settings? I was pointed to the website for the chipset that bladeRF uses but unfortunately for me the data was above my level of comprehension for the most part.

Phew! That's enough for now....thanks to anyone in advance!

[bpadalino]

bladeRF> calibrate
[WARNING] Never converged - DC_CLBR_DONE: 1 DC_LOCK: 0
[WARNING] Never converged - DC_CLBR_DONE: 1 DC_LOCK: 0

Can someone provide an explanation of exactly what this means? Also, are there any other commands that may further assist with reducing imaging and aliasing? I see a "correct" option but I'm not sure what "arguments" to provide, or if it would even help; it is pertinent to IQ imbalances.

What that means is that there was some internal calibration registers that were written, and DC_LOCK was supposed to be active when the DC_CLBR_DONE was also set. We are actively working on the calibration routines to build them into the frequency tuning and gain settings as well as remove that DC bias in general.

When it comes to the correction parameters, the doxygen documentation is the best to take a look at the bladerf_correction enum.

Finally, is there a "for dummies" in depth explanation of these commands available anywhere, and also for the various commands available to me via SDRConsole to include VGA1, VGA2, LPF, and LNA settings? I was pointed to the website for the chipset that bladeRF uses but unfortunately for me the data was above my level of comprehension for the most part.

If you're looking for help on the various CLI commands, typing 'help' is a good start. If you want to try different calibration routines, then you can try just typing 'help calibrate' and you should see:

Code: Select all

bladeRF> help cal

calibrate [<module>]

Calibrate the DC offset for both RX and TX

Available modules for calibration:

    tuning
    txlpf
    rxlpf
    rxvga2

Leave blank to calibrate all of the above.

The recommended order is listed on page 6 of the LMS6002D datasheet.

You should be able to do tuning, rxlpf and rxvga2 with no problem. Usually it's the txlpf that seems to give me a little trouble - though I am not sure why. We're working it.

This is a lot to digest. Let me know what other questions you may have.

Brian

[rowan.doherty]

I get a similar response:

Code: Select all

bladeRF> calibrate
[WARNING] Never converged - DC_CLBR_DONE: 1 DC_LOCK: 0
Error: An unexpected error occurred

I've also tried running the kalibration-bladeRF GSM calibration routine, but after it's given me the CAL value, I can't seem to write it to the device:

Code: Select all

average		[min, max]	(range, stddev)
-  45Hz		[-130, 14]	(145, 41.442207)
overruns: 0
not found: 0
Found lowest offset of -8.418392Hz at 944.400000MHz (-0.008914 ppm) using DAC trim 0x9c7a

Code: Select all

bladeRF> info

  VCTCXO DAC calibration:   0xfffc
  FPGA size:                115 KLE
  FPGA loaded:              yes
  USB bus:                  4
  USB address:              3
  USB speed:                SuperSpeed
  Backend:                  libusb
  Instance:                 0

bladeRF> flash_init_cal 115 0x9c7a
[INFO] Erasing 1 blocks starting at block 3
[INFO] Erased block 3
[INFO] Done erasing 1 blocks
[INFO] Writing 1 pages starting at page 768
[INFO] Writing page 768
[INFO] Done writing 1 pages
bladeRF> info

  VCTCXO DAC calibration:   0xfffc
  FPGA size:                115 KLE
  FPGA loaded:              yes
  USB bus:                  4
  USB address:              3
  USB speed:                SuperSpeed
  Backend:                  libusb
  Instance:                 0

Is the VCTCXO DAC calibration value meant to read "0x9c7a" after that command?

[jynik]

Is the VCTCXO DAC calibration value meant to read "0x9c7a" after that command?

After the flash_init_cal command, a power cycle is required for the new settings to take effect. The calibration settings are read from flash by the firmware when the device boots. I'll add a message to this command that states something to this effect.

As far as the calibration command goes, it's broken in master and we're actively working on DC calibration over the next few days. These changes will be pushed to the dev-cal branch on GitHub. I'll post back here when something usable is up there.

In the meantime, you could quickly dial things in manually, if need be..