Page 1 of 1

When is "ad9361_adc_xx_data" data valid?

Posted: Sun Feb 07, 2021 5:28 am
by Naper
Hi,
I have a BladeRF 2.0 A9. I would like to implement my code in the FPGA. My code, takes the I/Q samples of the RX0 and RX1 channels in input and processes them.

Studying the hdl of the BladeRF, I believe that the signals of my interest, in the case of channel i0, will be the following signals in output from the Nios II:

Code: Select all

ad9361_adc_i0_enable
ad9361_adc_i0_valid
ad9361_adc_i0_data
What I cannot understand, and would like to ask you, is the timing of the enable and valid signals.
When is "valid" activated? When is "enable" activated?
What is important for me is to understand when to get valid data from the AD9361. Or rather, understand when the data of the "ad9361_adc_i0_data" signal is valid.

note: I tried to simulate the behavior of the BladeRF with the Nios II using ModelSim, following the instructions in the AN 351 guide, and in the chapter 6.5 of the Embedded Design Handbook. Unfortunately I get an error when I go to generate "Create testbench simulation model". (maybe it's because I'm using the free version of Quartus)

Code: Select all

Error: arbiter_0: arbiter does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.
Error: Generation stopped, 20 or more modules remaining
Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings
Error: There were errors creating the testbench system.
I also tried to see the signals with the SignalTap, but it put me even more doubts, especially on the ad9361_adc_xx_valid signal.

Thank you.