bladeRF micro AD9361 LVDS Signals Used as Single-ended?

[rbschum]

I noticed that the AD9361 adi_rx(tx)_clock, adi_rx(tx)_frame, and adi_rx(tx)_data LVDS signals are all routed to the Cyclone V FPGA but internally, the FPGA treats them as single-ended by only using the "_p" signals. Does anyone know why that was done? Is there any reason they couldn't be used as LVDS pairs by the FPGA?

Thanks!

[robert.ghilduta]

The bladeRF 2.0 micro's HDL does use those pins in LVDS mode. The Altera LVDS HDL core only needs a reference to the positive (_p) LVDS pin. The negative (_n) counterpart is inferred by the LVDS HDL core because each positive pin only has one pin that can as its differential pair.

[rbschum]

Thanks for the reply, you are correct. I was confused by looking at the bladerf-hosted.vhd source code and for the nios_system component instantiation, the "_n" signals were either tied to '0' or open and that is what showed in the Quartus RTL Viewer. Taking another look at it with Quartus Technology Map Viewer - Post-Fitting, I see the differential IO_IBUFs and IO_OBUFs implemented for the LVDS signals as expected.