Minimize sampling jitter

Discussions related to schematic capture, PCB layout, signal integrity, and RF development
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jarek556
Posts: 6
Joined: Mon Oct 15, 2018 9:52 pm

Minimize sampling jitter

Post by jarek556 »

What is the best way to get stable sampling rate ? Can I use external clock providing directly sampling frequency, i.e 30.72MHz ?
robert.ghilduta
Posts: 156
Joined: Thu Feb 28, 2013 11:14 pm

Re: Minimize sampling jitter

Post by robert.ghilduta »

For a discussion on fundamental clock inputs and reference clocks, please take a look at https://www.nuand.com/frequently-asked- ... _reference . Basically the bladeRF 1.0 and bladeRF 2.0 should be able to take a certain kind of 38.4MHz as a fundamental clock input, and also the bladeRF 2.0 micro has an on-board ADF4002 PLL that can take the on-board 38.4MHz clock given a 10MHz reference.
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