Need some help with headless development.

Discussions related to embedded firmware, driver, and user mode application software development

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jynik
Posts: 455
Joined: Thu Jun 06, 2013 8:15 pm

Re: Need some help with headless development.

Post by jynik » Tue Feb 09, 2016 8:50 am

Jaco,

Excellent work! Anything you could share here would be vastly appreciated, I'm sure. I'd certainly like to make it easier for users to go down this path, be it through code changes, build scripts, documentation, etc.

Cheers!
Jon

dmetzger
Posts: 2
Joined: Thu Feb 02, 2017 9:23 am

Re: Need some help with headless development.

Post by dmetzger » Thu Feb 23, 2017 7:37 am

I've atempted to follow the above example. The Dual Clock FIFO has been added to the design but I do not receive what I transmitted into the device.

It also seems the tx_enable/rx_enable are never set to on even though peeking 0x40 and 0x70 returns the enable flag is on.

The below code is in the bladeRF_nios.c file, I set the gain once i'm in the cli.

Code: Select all

	//set bandwitdh 28Mhz
    lms6_write(0x54, 0x02);
    lms6_write(0x34, 0x02);


	//set samplerate 40Mhz
    //TX
    si5338_write(0x25, 0x01);
    si5338_write(0x40, 0xd7);
    si5338_write(0x41, 0x0d);
    si5338_write(0x42, 0x04);
    si5338_write(0x43, 0x00);
    si5338_write(0x44, 0x00);
    si5338_write(0x45, 0x00);
    si5338_write(0x46, 0x19);
    si5338_write(0x47, 0x00);
    si5338_write(0x48, 0x00);
    si5338_write(0x49, 0x00);
    si5338_write(0x20, 0xc0);
    //RX
    si5338_write(0x26, 0x03);
    si5338_write(0x4b, 0xd7);
    si5338_write(0x4c, 0x0d);
    si5338_write(0x4d, 0x04);
    si5338_write(0x4e, 0x00);
    si5338_write(0x4f, 0x00);
    si5338_write(0x50, 0x00);
    si5338_write(0x51, 0x19);
    si5338_write(0x52, 0x00);
    si5338_write(0x53, 0x00);
    si5338_write(0x54, 0x00);
    si5338_write(0x21, 0xc0);


    //TX/RXVGA1/2 gains (LMS)

    //LNA gain (LMS)

	//set tx/rx enable to on
	lms6_write(0x40, 0x01);
	lms6_write(0x70, 0x01);

	//Set NIOS GPIO state
    control_reg_write(0x00000057);


	//set frequency

    //RX
    lms6_write(0x20, 0x34);
    lms6_write(0x21, 0x15);
    lms6_write(0x22, 0x55);
    lms6_write(0x23, 0x55);
    lms6_write(0x25, 0x95);
    lms6_write(0x29, 0x86);
    //TX
    lms6_write(0x10, 0x34);
    lms6_write(0x11, 0x15);
    lms6_write(0x12, 0x55);
    lms6_write(0x13, 0x55);
    lms6_write(0x15, 0x95);
    lms6_write(0x19, 0x86);
Am I missing something? And am I right to assume these are the steps you would take to make an embedded design or is there an easier way to auto load frequency, sample rate, etc?

Jaco
Posts: 26
Joined: Wed Jul 30, 2014 2:03 am

Re: Need some help with headless development.

Post by Jaco » Fri May 05, 2017 11:09 am

dmetzger wrote:I've atempted to follow the above example. The Dual Clock FIFO has been added to the design but I do not receive what I transmitted into the device.

It also seems the tx_enable/rx_enable are never set to on even though peeking 0x40 and 0x70 returns the enable flag is on.

The below code is in the bladeRF_nios.c file, I set the gain once i'm in the cli.

Code: Select all

	//set bandwitdh 28Mhz
    lms6_write(0x54, 0x02);
    lms6_write(0x34, 0x02);


	//set samplerate 40Mhz
    //TX
    si5338_write(0x25, 0x01);
    si5338_write(0x40, 0xd7);
    si5338_write(0x41, 0x0d);
    si5338_write(0x42, 0x04);
    si5338_write(0x43, 0x00);
    si5338_write(0x44, 0x00);
    si5338_write(0x45, 0x00);
    si5338_write(0x46, 0x19);
    si5338_write(0x47, 0x00);
    si5338_write(0x48, 0x00);
    si5338_write(0x49, 0x00);
    si5338_write(0x20, 0xc0);
    //RX
    si5338_write(0x26, 0x03);
    si5338_write(0x4b, 0xd7);
    si5338_write(0x4c, 0x0d);
    si5338_write(0x4d, 0x04);
    si5338_write(0x4e, 0x00);
    si5338_write(0x4f, 0x00);
    si5338_write(0x50, 0x00);
    si5338_write(0x51, 0x19);
    si5338_write(0x52, 0x00);
    si5338_write(0x53, 0x00);
    si5338_write(0x54, 0x00);
    si5338_write(0x21, 0xc0);


    //TX/RXVGA1/2 gains (LMS)

    //LNA gain (LMS)

	//set tx/rx enable to on
	lms6_write(0x40, 0x01);
	lms6_write(0x70, 0x01);

	//Set NIOS GPIO state
    control_reg_write(0x00000057);


	//set frequency

    //RX
    lms6_write(0x20, 0x34);
    lms6_write(0x21, 0x15);
    lms6_write(0x22, 0x55);
    lms6_write(0x23, 0x55);
    lms6_write(0x25, 0x95);
    lms6_write(0x29, 0x86);
    //TX
    lms6_write(0x10, 0x34);
    lms6_write(0x11, 0x15);
    lms6_write(0x12, 0x55);
    lms6_write(0x13, 0x55);
    lms6_write(0x15, 0x95);
    lms6_write(0x19, 0x86);
Am I missing something? And am I right to assume these are the steps you would take to make an embedded design or is there an easier way to auto load frequency, sample rate, etc?
Hi,

I went down the same path for several days digging and modifying the NIOS processor code, but with no success whatsoever. There's something else that happens to begin streaming after the TX/RX modules are enabled, and I haven't been able to figure out how it works. Granted, it's been over a year since I've touched this project.

Back when I posted before, I ended up using GNURadio to enable / disable streaming & setup the frequency of the device. It required a small workaround to prevent libbladeRF from breaking with the modified FPGA image, but it worked just fine for what I was trying to do.

dmetzger
Posts: 2
Joined: Thu Feb 02, 2017 9:23 am

Re: Need some help with headless development.

Post by dmetzger » Fri Aug 25, 2017 5:41 am

I got it to work with GNU radio as well. I believe I added a simple DC FIFO then in the vhdl there was a signal with valid in the title that when 0 it transmitted to I channel, 1 to Q channel (or something like that). It was the only difficult change to find. There may have been other small changes to the enable signals. However I still can't get it to work embedded. In the end I may have to just add a separate controller for it, but I would assume I'm just missing a single element somewhere.

Jaco
Posts: 26
Joined: Wed Jul 30, 2014 2:03 am

Re: Need some help with headless development.

Post by Jaco » Mon Nov 20, 2017 5:49 am

dmetzger wrote:
Fri Aug 25, 2017 5:41 am
However I still can't get it to work embedded. In the end I may have to just add a separate controller for it, but I would assume I'm just missing a single element somewhere.
I have a feeling that it has something to do with the reference clocks generated by the Si5338.

I'm busy looking at output logs from running the CLI in verbose mode to figure out what exactly happens during TX and RX, it might be that some sample clocks are not active by default and you need to set them up manually. I haven't spent too much time on it but I'll post here if I can get some useful information out.

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