VHDL lms_rx_clock_out

[jay]

Hi All,

I have a process with a simple counter and when I run the code on the bladeRF, the output of the counter increments by 2 and there are also discontinuities in the counting at various multiples of 256. Is there anything I am missing on the functionality of lms_rx_clock_out?
here is my code for the process :

Code: Select all

	process(lms_rx_clock_out)
	begin
		if rising_edge(lms_rx_clock_out) then
			testing_variable<=testing_variable+1;
			if testing_variable=255 then
				testing_variable<=0;
			end if;
		end if;
	end process;

and my output is obtained by the following process

Code: Select all

		
    process(sys_rst, lms_rx_clock_out)
    begin
        if( sys_rst = '1' ) then
            rf_rx_fifo_sample <= (others => '0');
            rf_rx_last_sample <= (others => '0');
            rf_rx_sample_idx <= (others => '0');
            rf_rx_fifo_w <= '0';
        elsif( rising_edge(lms_rx_clock_out) ) then---caters for rising edge for all functionality
            if( dma_rx_en_rr = '1' ) then
            rf_rx_fifo_sample(31 downto 0) <= "0011" & to_signed(testing_variable, 12) & "1011" & to_signed(0, 12);
            rf_rx_fifo_w <= not lms_rx_iq_select;
            rf_rx_sample_idx <= rf_rx_sample_idx + 1;
            end if ;
        end if ;
    end process;

any help on this will be much appreciated.

[bpadalino]

The LMS clock is actually 2x the sampling frequency - one cycle transfers I and the other transfers Q.

More information on the interface can be found in the LMS6002D datasheet.

Hopefully that helps!

[jay]

thanx for the feedback, using a clock at half the sampling rate clears up the addition by 2 problem, however there are random instances where the counter skips values for instance a jump from 239 to 244.