I have the I/O board on my unit. It is not clear to me how to control these pins from Blade CLI. Is special FPGA code needed? Or does the standard FPGA code include a path to these pins? If issue has been addressed before, please let me know where. I would like to be able to wiggle an output pin from script file in Blade CLI.
Thanks Bruce NT4RT
I/O pins. Control??
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NT4RT
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- Location: Rock Hill, SC, USA
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jynik
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Re: I/O pins. Control??
Hi Bruce,
In the past, these had been available through some lower level programming interfaces and one would have to be familiar with the underlying FPGA I/O control registers.
I recently added some higher-level API functions for performing GPIO pin reads and masked writes. (The masked write leverages RMW operations being performed in the FPGA, alleviating the need to send two USB requests to first read the GPIO register, modify it, and then write the change back over USB.)
I just added some information here on the bladeRF-cli Tips and Tricks wiki page for you. If anything is not clear, let me know and we can further revise that entry.
As noted on this page, you'll need the latest code from master and FPGA v0.4.1 to use this. Are you using the Ubuntu PPA or familiar with building this code from source? If not, we can chat about getting you running the latest until this is included in the next release.
Best regards,
Jon
In the past, these had been available through some lower level programming interfaces and one would have to be familiar with the underlying FPGA I/O control registers.
I recently added some higher-level API functions for performing GPIO pin reads and masked writes. (The masked write leverages RMW operations being performed in the FPGA, alleviating the need to send two USB requests to first read the GPIO register, modify it, and then write the change back over USB.)
I just added some information here on the bladeRF-cli Tips and Tricks wiki page for you. If anything is not clear, let me know and we can further revise that entry.
As noted on this page, you'll need the latest code from master and FPGA v0.4.1 to use this. Are you using the Ubuntu PPA or familiar with building this code from source? If not, we can chat about getting you running the latest until this is included in the next release.
Best regards,
Jon