I'm currently seeing a huge peak at 422.4MHz, which is exactly CLK(38.4MHz)*11. The idea was to use a 10MHz CLK to see if we could rid of that specific peak, unfortunately I can't manage to set an external clock using bladeRF-cli:
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bladeRF> set clock_sel onboard
[VERBOSE @ host/libraries/libbladeRF/src/backend/usb/nios_access.c:429] nios_config_read: Read 0x00000001
[VERBOSE @ host/libraries/libbladeRF/src/backend/usb/nios_access.c:440] nios_config_write: Wrote 0x00000001
[VERBOSE @ host/libraries/libbladeRF/src/backend/usb/nios_access.c:429] nios_config_read: Read 0x00000001
Clock input: Onboard VCTCXO
bladeRF> set clock_sel external
[VERBOSE @ host/libraries/libbladeRF/src/backend/usb/nios_access.c:429] nios_config_read: Read 0x00000001
[ERROR @ host/libraries/libbladeRF/src/backend/usb/nios_access.c:77] Failed to receive NIOS II response: Operation timed out
[ERROR @ host/libraries/libbladeRF/src/board/bladerf2/bladerf2.c:3587] bladerf_set_clock_select: dev->backend->config_gpio_write(dev, gpio) failed: Operation timed out
Error: Operation timed out
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bladeRF> version
bladeRF-cli version: 1.9.0-0.2023.02-4build1
libbladeRF version: 2.5.0-0.2023.02-4build1
Firmware version: 2.4.0-git-a3d5c55f
FPGA version: 0.15.3 (configured from SPI flash)
Is it possible to reconfigure the VCTCXO to change it's base clock output ? Like change the 38.4MHz to a 31 or whatever would be in its possible range ?
Thanks,